AMD Accelerates CoWoP Transition; Rubin Ultra Expected Q2 Tape Out with 3nm and NVLink 576

NVDA-US is advancing its Rubin platform to full production while preparing the next-generation Rubin Ultra, expected to achieve tape-out in Q2 2026. The shift moves beyond 3nm ABF packaging to CoWoP, with Fanout-on-Substrate (fos) capabilities to be fully implemented in Q1 2026 at TSMC's Taichung facility, exclusively handling CoWoP trials. Key partners include TSMC (TSM), Chi Mei (4958-TW), and Xiamen Newstar (3037-TW), among others, expected to sample by Q1 2026. The Rubin Ultra, codenamed GR152, will support up to 576 GPUs via an expanded NVLink architecture to better match compute and interconnect needs for next-gen AI inference. PCB innovations, including SLP and mSAP on dual 7-layer HDI stacks with copper paste lamination, aim to close precision gaps and manage the signal integrity challenges brought by the increased pin count. TSMC is also adding a new oP process with solder spray to improve warpage and interconnect reliability, favoring solutions from Hynix (7751-TW) and possibly Wanheng (6187-TW). If successful, CoWoP adoption could become a standard packaging path for future AI chips beyond this generation.