TSMC Says Energy Efficiency Now Top Chip Design Constraint as AI Power Demand Soars

Amsterdam (Reuters) — Energy efficiency has overtaken raw computing power as the critical bottleneck in semiconductor design, driven by the massive electricity needs of artificial intelligence, a senior TSMC executive said on May 28, 2026. Kevin Zhang, TSMC’s senior vice president of business development, told a conference that clients—from smartphone makers to AI data center operators—now demand higher performance without increasing power consumption. “The area customers want to improve the most is energy efficiency,” Zhang said. He warned that simply adding more transistors is no longer enough. While boosting transistor density remains vital, advanced packaging, chip stacking and silicon photonics are gaining urgency. TSMC projects that from its current N2 process to the planned A14 node by 2028, power consumption can fall up to 30% with performance gains exceeding 20%. Zhang also dismissed Huawei’s newly proposed “Tau Scaling Law” as an incremental—not revolutionary—concept, saying 3D integration has been explored for years. TSMC manufactures AI chips for Nvidia and AMD, as well as custom processors for Google, Amazon, Meta and Microsoft.