Intel CTO Says 10x Advanced Wafer Capacity Unrealistic, Flags Supply Chain Limits

Intel Chief Technology Officer Pushkar Ranade said expanding advanced-node wafer output tenfold is unrealistic given the installed base of semiconductor manufacturing equipment, calling roughly a doubling more feasible. He made the remarks in a fab tour and executive interview published October 22 on the Dwarkesh Podcast. Ranade said bottlenecks extend beyond chip design and process scaling to upstream supply of extreme ultraviolet lithography, etch and thin-film deposition tools, which must grow in tandem with any capacity expansion. Intel executives also detailed the 14A process, in development for over three years and involving about 2,000 manufacturing steps, alongside High-NA EUV, backside power delivery, CFET and hybrid bonding work. On competition with TSMC (2330-TW), Ranade said fab scale, yield, customer ecosystem and on-time delivery matter as much as transistor density. He said Intel is technically competitive but must close a production-scale gap, adding that the industry must redesign cleanrooms and fabs to curb rising costs.